FIG. 1 (Prior Art) is a diagram of an alternating current to direct current (AC/DC) flyback constant voltage (CV) switching converter 1. A four-diode full wave rectifier 2 and an associated capacitor 3 converts a 110 volt amplitude alternating current (AC) signal across input leads 4 and 5 into a rough direct current (DC) on node 6. Node 7 is a relative ground for the DC voltage on node 6. Converter 1 works by rapidly switching switch 8 to be conductive and non-conductive. When switch 8 is conductive, a primary current 12 is made to flow from DC node 6, through the primary 9 of transformer 10, through the conductive switch 8, through sense resistor 11, and to ground node 7. As the primary current 12 flows, energy builds in a magnetic field in the transformer. Switch 8 is then made to be non-conductive. The collapsing magnetic field in the transformer causes a pulse of current 13 to flow in the secondary 14 of the transformer. This pulse of secondary current is rectified by diode 15 and capacitor 16 into a DC output voltage VOUT. The output voltage VOUT is present between output terminals 17 and 18. A voltage detector 20 detects the output voltage through a resistive voltage divider involving resistors 21 and 22. A controller integrated circuit 19 monitors the magnitude of the DC output voltage via voltage detector 20, an optocoupler 23, a conductor 24, and feedback terminal 25. Transformer 10 also has a third winding 26. When the flow of current in the primary is stopped, the collapsing magnetic field also causes a pulse of current to flow in auxiliary winding 26. This current is converted into a DC voltage on node 27 by rectifier diode 28 and capacitor 29. The supply voltage from node 27 powers the controller integrated circuit 19 via supply voltage terminal 30. The voltage developed across sense resistor 11 during the flow of primary current 12 is detected and used as an indication of peak primary current. Controller integrated circuit 19 has a current limit circuit that limits peak primary current by terminating the current pulse through the primary when the voltage across sense resistor 11 during a pulse of the primary current exceeds a predetermined voltage. This limit in the peak primary current serves to limit the maximum output power of the converter 1. Block 31 represents a load on the converter 1. The output current IOUT is the current that converter 1 supplies the load 31.
FIG. 2 (Prior Art) is diagram that illustrates an operation of the circuit of FIG. 1. In its CV mode, converter 1 attempts to maintain the output voltage VOUT across output leads 17 and 18 at a regulated output voltage VREG. VREG in this example is 5.0 volts. If, however, the load between output leads is so great that the converter would have to supply pulses of primary current that have peak currents above the preset current limit value, then the output voltage VOUT is not sustained at the desired VREG and the output voltage VOUT drops. When controller 1 is operating in CV mode, then converter operation is along line 90 of FIG. 2. When controller 1 is operating in current limit, then converter operation is along line 91 of FIG. 2.
FIG. 3 is a simplified waveform diagram that illustrates a first way that controller integrated circuit 1 might control switch 8 to regulate the voltage VOUT to VREG in the CV mode. This technique is referred to as “pulse width modulation”. If less energy should be transferred per unit time to load 31 into order to maintain the voltage VOUT at the regulated VREG value, then integrated circuit 19 narrows the pulses of the control signal supplied to switch 8. The left side of FIG. 3 illustrates the switch control signal with relatively wide pulses. The current in the primary 9 during an on-time of the switch is allowed to rise to a higher peak current value, and this high peak value results in a corresponding higher pulse of secondary current when the switch is turned off.
The right side of FIG. 3 illustrates the switch control signal with relatively narrow pulses. The current in the primary 9 during each on-time of switch 8 is not allowed to rise to as high of a peak current value as in the wide pulse situation. Accordingly, the current pulses induced into the secondary 14 are of lower magnitude as well. The controller integrated circuit 19 regulates the pulse width to maintain VOUT at the desired VREG.
FIG. 4 is a simplified waveform diagram that illustrates a second way that controller integrated circuit 19 might control switch 8 to regulate the voltage VOUT to VREG in the CV mode. This technique is referred to as “pulse frequency modulation”. If less energy should be transferred per unit time to the load 31 to maintain the voltage VOUT at the regulated VREG value, then integrated circuit 19 decreases the number of pulses per unit time supplied to switch 8. All the pulses are of the same width, so the magnitudes of the peak primary current during each switch on-time are the same, and the magnitudes of the induced pulses of secondary current are also the same. The number of such pulses per unit time, however, is varied to control the amount of energy supplied to load 31 per unit time such that VOUT is regulated to the desired VREG. The left side of FIG. 4 illustrates the switch control signal with a high frequency of pulses. The right side of FIG. 3 illustrates the switch control signal with a low frequency of pulses.
The pulse width modulation and pulse frequency modulation schemes have different advantages and disadvantages. There are parasitic capacitances represented in FIG. 1. Capacitor symbols 32-34 represent some of these capacitances. Each time switch 8 is turned on or turned off, these capacitances must either be charged or discharged. This charging and discharging represents a waste of energy. A way to reduce this wasted energy is desired.